Digital IC · RTL · SoC · Verification
Multi-Cycle RISC-V CPU / SoC
RV32E-oriented CPU RTL, valid-ready control, AXI/APB integration, memory models, reference-model comparison, and engineering debug.
View project →Projects
Projects
A closer look at the circuits, processors, and hardware I have worked on, with design details and results.
Analog IC · Full-Custom Layout
Class-AB Audio Amplifier
Independent GF 0.18 µm schematic-to-layout design with DRC/LVS/PEX and documented pre-/post-layout simulation evidence.
View project →RTL · Synthesis · STA · Place & Route
NM6008 Digital IC Design Lab
Introductory course exercises using GF 22 nm libraries: basic logic cells, Verilog, synthesis, timing analysis, and place and route.
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RF Hardware · Simulation · Measurement
Interdigital SSPP Low-Pass Filter
First-author research connecting CST design, PCB prototyping, VNA measurement, publication, granted patent, and undergraduate thesis.
View project →Embedded · PCB · Hardware Bring-Up
Multi-Vehicle Smart Car Hardware
Verified personal contribution in PCB work, assembly, communication integration, PID tuning, and system-level debugging.
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Analog IC · Early Coursework
Bandgap-Based Reference Circuit
An earlier TSMC 0.18 µm schematic and pre-layout simulation exercise, retained with explicit limitations and lower portfolio priority.
View project →Competition demos
Multi-Vehicle Formation
National Second Prize, 17th National College Student Smart Car Competition
TI Cup: Dual-Vehicle Following
Two cars coordinate their movement using line sensors, ultrasonic ranging, and Bluetooth. Awarded First Prize in Jiangsu.