Digital IC · RTL · SoC · Verification

Multi-Cycle RISC-V CPU / SoC

An ongoing personal engineering project built within the YSYX training ecosystem. I implement the CPU and major project-specific hardware while separating upstream frameworks and third-party IP.

RISCV32 repository ysyxSoC repository

Architecture

The CPU follows the RV32E ISA/ABI and uses IF, ID, EX, LSU, and WB functional stages. Valid-ready handshakes allow variable-latency memory transactions.

Role: Main hardware designer and implementer for the personal CPU/SoC project
Status: Ongoing development and learning
HDL / Software: Verilog, SystemVerilog, Chisel, C, C++, RISC-V assembly

Functional architecture of the multi-cycle RISC-V CPU — CPU functional architecture showing IFU, IDU, EXU, CSR, register file, LSU, and WBU. Stage labels describe control flow, not a pipelined implementation.

Difftest · Waveform

NEMU difftest and RTL debug

Reference-model comparison using NEMU, Verilator, FST/GTKWave, AM tests, riscv-tests, custom programs, and trace-based debugging. No coverage or pass-rate metric is claimed.

What I implemented or adapted

RV32E-oriented integer instruction control, branches, jumps, and byte/halfword/word loads and stores.
CSR access, ECALL, MRET, and related trap entry/return control; complete precise-exception support is not claimed.
CPU-side AXI arbiter plus integration with the official ysyxSoC AXI/APB ecosystem.
SDRAM and QSPI PSRAM behavioral models, controller adaptation, width expansion, timing debug, Flash/XIP and bootloader work.

Debugging evidence

Investigated CAS latency, burst length, read-data and rvalid timing in the SDRAM path.
Found and debugged address mirroring and Bank/Row control issues.
Worked on Flash-to-external-memory loading, linker layout, and RT-Thread image startup/run debugging. A final successful runtime configuration is not claimed.

Attribution and limitations

NEMU, Abstract Machine, the official ysyxSoC interconnect, Rocket-Chip Diplomacy, base memory controllers, and the PS/2 receiver include upstream or third-party work. Claims are limited to traceable implementation, modification, adaptation, integration, and debugging; no hardware M extension, cache/MMU, FPGA validation, complete ISA coverage, performance, area, or frequency result is claimed.